The Core of Innovation

Intermolecular and New Materials Discovery

by Amelia Dalton

The journey is not an easy one. Most engineers can't even see the finish line, let alone complete the race. The future of our industry hangs in balance and this is a competition that must be won - one way or another. In this week's fish fry, we investigate the perilous path to new material discovery with Chris Kramer of Intermolecular. Chris and I discuss the materials discovery process, the subtle interaction between process tools and new materials, and the challenges and opportunities new materials can bring. Also this week, we take a closer look at a new type of 3D printed material developed at the Hasso-Plattner-Institute, in Potsdam, Germany that can make simple machines out of 3D printed plastic.  Read More


Industry News

September 23, 2016

TSMC and Synopsys Collaboration Delivers Innovative Technologies for the High Performance Compute (HPC) Platform

Pasternack Introduces New Lines of RF and Microwave Waveguide Directional Couplers

Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms

September 22, 2016

Mouser Now Stocking the Low-Power Intel® Curie™ Module for Wearable and Edge Devices

Avnet and Arizona State University Seek Nation’s Next Technology Entrepreneurs

Saelig Introduces 5-in-1 PC-Hosted Test Scope With Signature Analysis

AVX Adds 26VDC Components to its Proven, Dual-Function TransFeed™ & TransFeed Automotive Series Varistors

40VIN, 2.1A Rail-to-Rail LDO+ Now Offered in High Temp, 150°C H-Grade in TSSOP Package

Antenna Company Launches High Performance SuperShape® Antenna for Telematics Applications

September 21, 2016

Cadence Delivers Rapid Adoption Kit for Fast Implementation and Signoff of New ARM Cortex-R52 CPU

STMicroelectronics Promotes New Digital Age in India

eSilicon revolutionizes semiconductor IP selection and purchasing

Synopsys and TSMC Collaborate to Certify Custom Compiler for 16FFC Process

Altium CircuitStudio v1.2 now available exclusively from element14 via eDelivery

Pervasive Displays collaborates with Energia IDE to add ultra-low power e-paper driver support to TI LaunchPad™ development kits

Mentor Graphics Extends Offering to Support TSMC 7nm and 16FFC FinFET Process Technologies

Dual µModule Regulator in 15mm x 9mm x 2.42mm BGA is Configurable as SEPIC (Buck-Boost) and Inverting

EMA Provides Supply Chain Driven Part Selection with New PLM and ERP Integrations for the OrCAD Solution

Samsung SDS Selects Sensory as Biometric Partner

Synopsys Foundation IP Meets Stringent Automotive AEC-Q100 Grade 1 Temperature Requirements for TSMC 16FFC and 28HPC+ Processes

September 20, 2016

Synopsys Accelerates Development of Safety-Critical Products with Design Solutions for ARM Cortex-R52

Real Intent Sets a New Benchmark in Early Verification of Digital Designs with Release 2016.A of Ascent Lint

Quantum 2.0 has potential to create step change in computing and communications

UltraSoC supports RISC-V: “the Linux of the semiconductor industry”

General Micro Systems Introduces Latest Fully Isolated, Rugged Multi-Domain Red/Black Server with Intel® Xeon® D and Removable Drives

News Archive

Tell Me What to Think

The Crayon Effect and New Product Development

by Jim Turley

Xilinx vs Intel

The New Showdown in Programmable Logic

by Kevin Morris

Interim Industrial Security

Icon Labs Firewalls Grandpa Equipment

by Bryon Moyer

The Only Dot You Will Ever Need

Iota Labs Takes on Physical Push Notifications

by Amelia Dalton

Articles Archive

 

 

forum

Intel’s First FPGAs

Posted on 09/24/16 at 12:23 PM by KarlS51

It is about time to quit building things from such tiny pieces such as wiring segments and single FFs as that requires too much P&R.

CPUs have been using microcode for generations and many features and bug fixes have been done just with new microcode.

Intel’s First FPGAs

Posted on 09/21/16 at 12:45 AM by TotallyLost

TotallyLost
HLL to gates at the 95% level is much easier than one might guess ... although there are parts of some HLL's that do not map well (dynamic allocation in C++ and JAVA, arbitrary pointers in C, etc). I spent a few years at that problem with FpgaC, and made …

Xilinx vs Intel

Posted on 09/20/16 at 4:22 PM by KarlS51

"nothing would be better than a tool suite that could take a legacy C/C++ software application and magically create an optimized, accelerated version that executed on a conventional processor paired with FPGA fabric. Such a tool does not exist, however, n…

Interim Industrial Security

Posted on 09/19/16 at 1:47 PM by bmoyer

bmoyer
What do you think of Icon Labs' approach to securing old networked industrial equipment?

Humans vs. Computers

Posted on 09/19/16 at 8:04 AM by dbrower

Of course if they are using internet available data to authenticate, well hummm. And Yes, I'm old enough that my childhood address is probably not on the internet but that's probably not true for a majority already. As we lose more and more privacy to …

Humans vs. Computers

Posted on 09/15/16 at 1:41 PM by bmoyer

bmoyer
I'm really amazed they didn't have alternative ways of confirming that you're you. There are services that some banks, for instance, use. They present, oh, three past addresses and ask which one is yours. The bank doesn't know the right answer; they just …

Forum Archive

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Featured Blogs

Xilinx, Inc.

September 24, 2016
  The video in this post on the Lightreading.com Web site shows Napatech’s Don Joe Barry discussing the acceleration provided by his company’s NFV NIC. Briefly, the Napatech NFV NIC reduces CPU loading for NFV applications by a factor of more than 7x…
 

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EE Journal Marketing Insider

September 23, 2016
We all know that it is important to generate useful content. Not only does your content need to be well written, but also your audience must find your topics important enough to justify their time spent reading it. One of the ways they make their…
 

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Element14

September 22, 2016
IntroductionThis blog post is about powering a new security camera (HAL-CAM 9001) using network cables. These could be cables already installed in an office or home environment, saving costs, or they could be new cables installed indoors or outdoors (usin…
 

More from Element14...

Samtec, Inc.

September 21, 2016
Engineers love samples.  They often choose the right pin count, pitch, stack height, orientation or other design criteria based on what they see and feel.   Samtec leads the industry in providing the connector samples engineer needs in a timely manner.  O…
 

More from Samtec, Inc....

EE Journal Editors' Blog

September 14, 2016
With the growth of the IoT there is increased interest in the overlapping areas of safety and security. There is already a lot of knowledge on these issues and this has been shared by the IET's International System Safety and Cyber Security Conference. Th…
 

More from EE Journal Editors' Blog...

Featured Blogs Archive

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chalk talks

Targeting SDR Design to Hardware

Software defined radio (SDR) design is a complex dance of hardware and software. In this episode of Chalk Talk, Amelia Dalton chats with Noam Levine from MathWorks about how to simplify the implementation of SDR in hardware.

Six Hidden Costs of Wireless SoC Design

Modules offer an attractive alternative to wireless SoCs in many situations. In this episode of Chalk Talk, AD chats with Joe Tillison from Silicon Labs about six hidden costs of doing a wireless SoC design.

Introducing Kinetis Motor Suite

Do you want to design in a motor without having to become an expert in motor control? In this episode of Chalk Talk, Amelia Dalton chats with Phillip Drake of NXP about simplifying motor control with Kinetis. It'll have your motor spinning in no time.

Addressing the Challenges of Serial Link Design and Analysis

High-speed serial interfaces present some of the biggest challenges in board design today. Getting signal integrity right on your board with speeds into the gigabits can be tricky at best. In this episode of Chalk Talk, Amelia Dalton chats with Brad Griffin of Cadence Design Systems about using Cadence's Sigrity analysis tool to nail your next serial interface design.

One Time Programmable OmniClock Generators

Are you tired of dealing with too many clocks in your design? This episode of Chalk Talk can help. Amelia Dalton chats with Eduardo De Reza from ON Semiconductor about OmniClock, which can help you to tame that wild pack of clocks once and for all.

Introduction to the New Virtuoso ADE Product Suite

Do different members of your team have different requirements and challenges for your analog design tools? In this episode of Chalk Talk, Amelia Dalton chats with Steve Lewis of Cadence Design Systems about the new capabilities in Cadence's Virtuoso ADE Product Suite - capabilities that will make everyone on your team happy.

Chalk Talk Archive


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