Xilinx Previews Next Generation

New Xilinx CEO Victor Peng made his public debut by sketching out the latest vision for the world’s leading FPGA company last week, and it included a bold claim – that Xilinx was inventing an entirely new category of semiconductor device, the Adaptive Compute Acceleration Platform (ACAP). We’ll say right up front that there is precious little information available on these future devices; the first examples of them … Read More → "Xilinx Previews Next Generation"

When Lives Depend on Your Machine-Learned Model

“How to validate training data is an open question that might be addressed by some combination of characterizing the data as well as the data generation or data collection process.”
‘Challenges in Autonomous Vehicle Testing and Validation’, Koopman and Wagner, 2016

Last summer, we published a piece on safety-critical capabilities in EDA. … Read More → "When Lives Depend on Your Machine-Learned Model"

Real World ATCA and SWAP-C, a Revolution in Gaming, and Bathtub Drones

Welcome my electronic engineering compatriots! We’ve got quite a line up for you this week. First up, Rob Persons (Artesyn Embedded Technologies) joins us to discuss the details of a real world AdvancedTCA application that utilizes SWAP-C called DASCAN (Dynamically Adaptive Secure Computing Area Network) and how AdvancedTCA applications compare with more traditional server-based applications in battlefield environments. We also discuss how Artesyn has collaborated with Gamestream and … Read More → "Real World ATCA and SWAP-C, a Revolution in Gaming, and Bathtub Drones"

Decoding Silicon Valley

“Silicon Valley is not a magical place, but magical things happen there.” – Jonathan C. Baer

Earlier this week, more than 100 engineering consultants, a few marketers, and four mad scientists (self-proclaimed “consulting physicists”) met under the auspices of the IEEE-CNSV—that’s the Consultants’ Network of Silicon Valley—to schmooze, eat Stuft pizza, and hear serial … Read More → "Decoding Silicon Valley"

Xilinx Strikes Back – Kinda

This week, Xilinx hit us with a duo of SerDes-related announcements – a demonstration of 112G PAM4 electrical signaling technology for optical networks, and the addition of 58G PAM4 transceivers to some of their 16nm Virtex® UltraScale+™ devices. The announcements were made at the Optical Fiber Communication Conference and Expo (OFC 2018), where Xilinx demonstrated what they claim are the industry’s first 112G PAM4 transceivers. (We think they mean “first … Read More → "Xilinx Strikes Back – Kinda"

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Posted on Mar 20 at 12:05pm by Ura
Right on the money BKM! All of these heterogeneous computing "solutions" aren't complete until they can be used in common software development environment. OpenCL and Cuda don't count in this regard. It can be done, but I'm skeptical that semiconductor companies can make that part happen. I think some smart ...
Posted on Mar 20 at 11:21am by Beercandyman
It's nice that they are talking about the data center. It's a huge market. Their story is "use our parts to accelerate your software" but they don't use their parts to accelerate their own software. Until an FPGA manufacturer goes through the exercise of accelerating their own software they will ...
Posted on Mar 20 at 6:41am by Kevin Morris
What do you think about Xilinx's new vision and ACAP? Will they challenge NVidia's lead in the data center acceleration market? How will it stack up against Intel/Altera's "Falcon Mesa"? (We'll have a follow-up article on this exact topic very soon.)
Posted on Mar 19 at 10:56am by Bryon Moyer
How do you approach machine-learned model validation?
Posted on Mar 16 at 1:48am by inovelpwnz
make sense, altho not a single mention of crypto (currency). that one definetely will have its place
Posted on Mar 15 at 2:45am by inovelpwnz
its great. but what does it all mean for consumers? the transition from finfet to GAA the annual 5% increase in synthetic work?
Posted on Mar 12 at 4:11pm by Bryon Moyer
You're right! Good catch; thanks. Updated to fix it.
Posted on Mar 12 at 1:27pm by mcgett
Something is wrong with data in the "6T SRAM Cell Area" row, either the data has been swapped between the Intel and GF columns or the ratio should be 1.16 not 0.86.
Posted on Mar 12 at 9:40am by Bryon Moyer
What do you think about these platforms? And the nodes they're named after?
Posted on Mar 5 at 10:03am by Bryon Moyer
What do you think of DSP Concepts' approach to low-level audio design?
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chalk talks
ANSI/VITA 57.4-2016 FMC+ — The New Frontier of FPGA Expansion CardsFPGA Mezzanine Cards (FMC and FMC+) allow easy connection of a wide variety of peripherals to FPGA development boards. But, FMC – and particularly FMC+ put big demands on connector technology. In this episode of Chalk Talk, Amelia Dalton chats with Matthew Burns of Samtec about FMC and FMC+ standards, and the connectors that make … Read More → "ANSI/VITA 57.4-2016 FMC+ — The New Frontier of FPGA Expansion Cards"
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Mid-Board Optics: An Alternative to Pluggable MSA Solutions How would you like to upgrade from copper to optical flyover – all with the same connector system? In this episode of Chalk Talk, Amelia Dalton chats with Matthew Burns from Samtec about Firefly – a future-proof high-density flyover system. Click here to download the Firefly Application Design Guide
Mixed-Signal Digital Complexity Explosion   Mixed-signal design is becoming increasingly complex, and our old tools and methods just won’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe of Cadence Design Systems about the changing mixed-signal landscape and how Cadence’s robust suite of mixed-signal design solutions can solve your toughest problems. Click here … Read More → "Mixed-Signal Digital Complexity Explosion"
Intel® Aero Ready to Fly Drone In order to develop new applications for drones, we need a flying development kit. Drones are complex systems with incredible versatility, and developing software and hardware can be tricky. In this episode of Chalk Talk, Amelia Dalton chats with Paul Guermonprez of Intel about a new drone development ecosystem. Click here for more information … Read More → "Intel® Aero Ready to Fly Drone"
Moving Between FPGA and ASIC with High-Level Synthesis Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow. Click here for more … Read More → "Moving Between FPGA and ASIC with High-Level Synthesis"