Overview

Reinventing Multi-Chiplet Design

The Cadence® Integrity™ 3D-IC Platform is the new high-capacity, unified design and analysis platform for designing multiple chiplets. Built on the infrastructure of Cadence’s leading digital implementation solution, the Innovus™ Implementation System, the platform allows system-level designers to plan, implement, and analyze any type of stacked die system for a variety of packaging styles (2.5D or 3D). Integrity 3D-IC is the industry’s first integrated system- and SoC-level solution that enables system analysis, including co-design, with Cadence’s Virtuoso® and Allegro® analog and package implementation environments.

Key Benefits

Enabling a Faster Path to Multi-Chiplet Design Closure with Better Predictability

Productivity

Engineers can plan and build multiple chiplets in a unified environment simultaneously with a multi-technology database

Design Robustness

Integrated electrothermal and physical checks to ensure reliability

System-Driven PPA

Early feedback from system-level analysis to improve chip-level power, performance, and area

Ease of Use

Single planning cockpit and hierarchical database allows interactive flow management and results analysis

integrity 3d-ic platform

The Industry’s First Integrated 3D-IC Platform

Integrity 3D-IC Graphic Diagram

use models

Supported Advanced Packaging Configuration

  • Fan-out wafer-level packaging (FOWLP) with integrated fanout
  • RDL and silicon interposer (2.5D)
  • Wafer on wafer, chip on wafer
  • Full 3D stacking

Features

Addressing the Requirements of 3D-IC Planning, Implementation, and Analysis for Digital, Mixed-Signal SoCs, and Entire 3D Stacks

  • Complete 3D planning system: Incorporates a complete 3D-IC stack planning system for all types of 3D designs, enabling customers to manage and implement 3D stacking
  • Seamless integration with Innovus Implementation: Provides ease-of-use through direct script-based integration with the Innovus Implementation System for high-capacity digital designs with 3D die partitioning, optimization, and timing flows
  • Integrated system-level analysis capabilities: Enables robust 3D-IC design through early electrothermal and cross-die static timing analysis (STA), which allows early system-level feedback for system-driven PPA
  • Common cockpit and database: Lets SoC and package design teams co-optimize the complete system concurrently, allowing system-level feedback to be incorporated efficiently
  • Native 3D: Enables users to uniquely partition a 2D design into a 3D multi-tier design using 3D mixed placer technology
  • Co-design with analog and packaging platforms: Allows engineers to seamlessly move design data to various parts of the system through the hierarchical database, enabling faster design closure and improved productivity
  • Easy-to-use interface: Includes a powerful user cockpit that allows interactive results analytics and run management capabilities to gain valuable insights into design metrics

Related Solutions

Enabling Customers to Achieve System-Driven PPA, Reduced Design Complexity, and Faster Time to Market

3D-IC Design

Advanced-Node Design

Resources

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