Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.
Cadence Blog – Latest Posts
The Next Leap in AI and CFD Simulation: Co-Optimization from Cadence and NVIDIA
Innovation in the AI and supercomputing domains is proceeding at a rapid pace, with each new advancement heralding a future more tightly interwoven with the threads of intelligence and computation. Cadence, with the release of its Millennium Platform, co-optimized with NVIDIA...
Spectre Tech Tips: Spectre S-Parameter Quality Checking and Fitting Tool
In Spectre, the nport element allows users to include S-Parameter data for time and frequency domain circuit simulation. At times, Spectre users face convergence or performance problems when the S-Parameter data has poor quality. The typical S-Parameter issues that might caus...
Celebrating the Wonders of Pi Day: A Journey into Mathematics and Beyond
Mathematics is a universal language, understood and appreciated in every corner of our ever-inquisitive world. March 14 is recognized as Pi (π) Day by mathematicians and enthusiasts worldwide to acknowledge the significance of Pi, which has been an unwavering ally in humanit...
The Evolution of the Olympics: Tracing the Arc of Technological Innovation
2024 Paris Summer Olympics The Olympics, a hallowed tradition with roots in ancient Greece, transitioned into the modern era in 1896 and has since seen a remarkable influence of technology, revolutionizing arenas, equipment, and the very fabric of the games. From the humble b...
Jumpstarting the Automotive Chiplet Ecosystem
The automotive industry stands on the cusp of a technological renaissance, ushering in an era where vehicles aren't just tools of transportation, but interconnected nodes within a vast network of software-defined mobility. Central to this transformation is the concept of...
Video Search Tips - Get the Most Out of the Cadence Learning and Support Portal
As you might have seen already, we recently published “Get the Most Out of the Cadence Learning and Support Portal” blog , and hopefully, the training was helpful in getting a deeper knowledge about the Cadence Learning and Support (COS) portal and its multiple features. ...
Unveiling the Blueprint for Next-Gen SoC with Cadence Tools
Insights From a Conversation With Matti Käyrä of SoC Hub, Finland The relentless pursuit of innovation in the intersection of technology domains such as AI, imaging, and security has become the hallmark of next-generation systems-on-chip (SoCs). At the heart of this...
With MemVerge Cadence Innovus Now Spot Instance Ready!
The pursuit of efficiency in cloud computing has led industries to innovate resource consumption, with Amazon EC2 Spot Instances emerging as a cost-effective choice for high-performance computing (HPC ) and Electronic Design Automation (EDA). Amazon web services (AWS) EC2 Spo...
Chalk Talks Featuring Cadence
Faster, More Predictable Path to Multi-Chiplet Design Closure
The challenges for 3D IC design are greater than standard chip design - but they are not insurmountable. In this episode of Chalk Talk, Amelia Dalton chats with Vinay Patwardhan from Cadence Design Systems about the variety of challenges faced by 3D IC designers today and how Cadence’s integrated, high-capacity Integrity 3D IC Platform, with its 3D design planning and implementation cockpit, flow manager and co-design capabilities will not only help you with your next 3D IC design.
Enabling Digital Transformation in Electronic Design with Cadence Cloud
With increasing design sizes, complexity of advanced nodes, and faster time to market requirements - design teams are looking for scalability, simplicity, flexibility and agility. In today’s Chalk Talk, Amelia Dalton chats with Mahesh Turaga about the details of Cadence’s end to end cloud portfolio, how you can extend your on-prem environment with the push of a button with Cadence’s new hybrid cloud and Cadence’s Cloud solutions you can help you from design creation to systems design and more.
Machine-Learning Optimized Chip Design -- Cadence Design Systems
New applications and technology are driving demand for even more compute and functionality in the devices we use every day. System on chip (SoC) designs are quickly migrating to new process nodes, and rapidly growing in size and complexity. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe about how machine learning combined with distributed computing offers new capabilities to automate and scale RTL to GDS chip implementation flows, enabling design teams to support more, and increasingly complex, SoC projects.
Cloud Computing for Electronic Design (Are We There Yet?)
When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.
Featured Content from Cadence
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Faster Path to Multi-Chiplet Design Closure with Better Predictability
Discover how Cadence Integrity 3D-IC is reinventing multi-chiplet design. The Integrity™ 3D-IC Platform provides an industry-first holistic and comprehensive 3D-IC design planning, implementation, and analysis platform to take the full system view and perform system-driven optimization of performance, power, and area (PPA) for chiplets and co-design of interposers, packages, and PCBs for 3D-IC applications
featured paper
3D-IC Design Challenges and Requirements
While there is great interest in 3D-IC technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is in flux, and design, analysis, verification, and test challenges need to be resolved. Read this paper to learn about design challenges, ecosystem requirements, and needed solutions. While various types of multi-die packages have been available for many years, this paper focuses on 3D integration and packaging of multiple stacked dies.
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Dramatically Improve PPA and Productivity with Generative AI
Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.
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Industry’s First LLM Technology for Chip Design
Read about the first robust proof of concept of a large language model (LLM) in chip design. To focus on this LLM’s conversation skills would be to misunderstand just how powerful this technology stands to be in solving some of chip design’s most pressing challenges—automating the workflow to reduce errors introduced by humans in creating the design specification, the design itself, and all the project documents needed to create a complex semiconductor device.