February 13, 2017
Coventor Unveils New Scientific Findings on Lithography Processing For Improved Semiconductor Scalability and Performance
At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices
CARY, NC-- February 13, 2017 - Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will present findings from its research on advanced semiconductor fabrication processes at SPIE Advanced Lithography 2017. The results of these studies provide insight into techniques for advancing the state-of-the-art in semiconductor technology through use of new and emerging photomask, lithography and process technologies.
“The semiconductor industry is continually striving to scale device performance and density up while driving costs down,” said Dr. David Fried, CTO of Coventor. “With advances in lithography, processing techniques and device architectures, being able to predict the structural behavior of complex 3D devices before any physical wafers are fabricated is essential. Internally within Coventor and around the industry with our partners, virtual fabrication using our SEMulator3D modeling platform is demonstrating the ability to increase semiconductor device density and yield through control of process variation.”
Coventor conducted a series of studies aimed at understanding semiconductor lithography and manufacturing issues that could affect yield and device density at future technology nodes (N7 and lower). Coventor and its partners will present findings from these studies in three presentations at this year’s SPIE Advanced Lithography conference.
In one of its studies, Coventor worked with a team from Imec to compare the effects of variability on different semiconductor fabrication processes. The team used Coventor’s SEMulator3D process modeling software to simulate the fabrication of hundreds of virtual semiconductor wafers, in an attempt to improve advanced semiconductor processing techinques. They used modeling data to compare self-aligned and fully-self-aligned semiconductor via processes, using a calibrated model for Imec’s N7 BEOL processing technology. The results indicate that fully self-aligned vias provide better metalization and contact area control, leading to higher density semiconductor devices. Coventor’s findings from its work with Imec will be presented in a session entitled “EPE Analysis of sub-N10 BEOL structures with Coventor’s SEMulator3D” (Paper 10145-81, Tuesday, February 28, 2017 at 6:00 to 8:00 pm).
Another Coventor study will be presented in a session entitled “Investigation of 3D Photoresist Profile Effect in Self-Aligned Patterning Through Virtual Fabrication” (Paper 10147-15, Tuesday, February 28, 2017 at 4:10 to 6:00 p.m.). In this study, the authors analyzed the effects of photoresist sidewall profile and line edge roughness on both front-end of line (FEOL) and back-end of line (BEOL) lithography schemes. The authors determined that the electrical characteristics and expected device density of advanced semiconductor devices (such as FinFETs) will be negatively impacted during semiconductor manufacturing, unless tight exposure and development controls for these parameters are in place during semiconductor production.
Thirdly, Dr. David Fried will present a keynote session titled: “Technology Development: the "In Between" (Paper 10147-1, Tuesday, February 28, 2017 at 8:40 - 9:20 am). Dr. Fried will discuss the risk and complexity of the time “in between” research ideas, new technologies and actual products in the semiconductor industry, and review ideas for addressing these challenges.
Coventor and its customers have been using virtual fabrication to deepen the understanding of what’s required to incorporate new lithography technologies. The latest version of Coventor’s SEMulator3D Virtual Fabrication Platform enables process modeling for FinFETs, 3D NAND Flash, BEOL, Nanowires, 3D-IC, FDSOI, DRAM, and other next generation processes. The company will demonstrate the latest version of its SEMulator3D Virtual Fabrication Platform, in its booth (#306).
SPIE Advanced Lithography is the premier conference for the lithography community. For over 40 years, SPIE has brought together this community to address challenges presented in fabricating next-generation integrated circuits.
Coventor, Inc. is the market leader in automated design solutions for developing semiconductor process technology, as well as micro-electromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, memory suppliers, fabless design houses, independent foundries, and R&D organizations. Its SEMulator3D modeling and analysis platform is used for fast and accurate ‘virtual fabrication’ of advanced manufacturing processes, allowing engineers to understand manufacturing effects early in the development process and reduce time-consuming and costly silicon learning cycles. Its MEMS design solutions are used to develop MEMS-based products for automotive, aerospace, industrial, defense, and consumer electronics applications, including smart phones, tablets, and gaming systems. The company is headquartered in Cary, North Carolina and has offices in California’s Silicon Valley, Waltham, Massachusetts, and Paris, France. More information is available at http://www.coventor.com.