What do high level synthesis, FPGAs, and the first 3D printer capable of printing fully-functional electronics have in common? This week’s podcast, of course! First up, I chat with Max Odendahl (CEO, Founder – Silexica) about ins and outs of system level understanding and optimization, what we can do with unsynthesizable C/C++ code and how we can tackle the biggest challenges in using Software (C/C++) for hardware … Read More → "Driving Optimization"
In a recent Cool Beans column — What the FAQ are the IoT, IIoT, IoHT, and AIoT? – I introduced the concepts of the cloud, the fog, … Read More → "What the FAQ is the Edge vs. the Far Edge?"
In part 1 of this series, we looked at new high-end FPGA families from Xilinx, Intel, and Achronix and discussed their underlying semiconductor processes, the type and amount of programmable logic LUT fabric, the type and amount of DSP/arithmetic resources and their applicability to AI inference acceleration tasks, the claimed TOPS/FLOPS performance capabilities, and on-chip interconnect … Read More → "High-End FPGA Showdown – Part 3"
“It’s like déjà vu all over again.” – Yogi Berra
Dude, this is so trippy. It’s like a flashback to the 1970s. Where’s my TTY Model 33?
The upshot: Trained AI models have to be adapted for specific inference implementations. New inference hardware was presented at Hot Chips by Intel, Xilinx, and Nvidia, and Mipsology has yet another inference option.
This week we bring the natural follow-on to the machine-learning (ML) training piece of Read More → "SoCs for ML Inference"
There are many roads to prosperity, but one must be taken. Inaction leads nowhere. – Robert Zoellick
Security is not implemented overnight. Standards don’t create themselves. And our design lives won’t get easier if security and standards aren’t addressed at every step of the game. In this week’s podcast, Brent Sherman (Intel), Adam Sherer (Cadence) and I chat about the challenges of … Read More → "Plotting a Course to Functional Safety"
