AI is My Copilot: How Flux is Revolutionizing PCB Design

My podcast guest this week is Mattias Wagner from Flux! Mattias and I investigate the role that AI plays in the Flux PCB design platform. We also delve into the details of the Flux Method, Flux Model and Flux Copilot, and discuss why working smarter not harder is cornerstone to the Flux mission. I also investigate why the discovery of phosphorus in … Read More → "AI is My Copilot: How Flux is Revolutionizing PCB Design"

Honey, I Shrunk the Switching Regulator (into a 2.2 x 1.6 mm footprint)

Shrink rays are a common trope with a long history in science fiction. The first time I saw one “in use” was in the 1966 film Fantastic Voyage and Isaac Asimov’s book based on the film’s screenplay. In Fantastic Voyage, movie and book, the shrink ray is used to miniaturize a submarine named Proteus so that it can be injected … Read More → "Honey, I Shrunk the Switching Regulator (into a 2.2 x 1.6 mm footprint)"

Synopsys Takes on RISC-V Configurability with ARC-V Processor IP Family

Long, long ago, at the turn of the millennium, two champions of configurable processor IP – ARC and Tensilica – battled for dominance in that arena with unique processor ISAs and custom tools to aid in creating software-development tool chains for their configurable processors. Synopsys bought ARC in 2011, and Cadence bought Tensilica a couple of years later. Fast forward a decade and suddenly, RISC-V has somehow validated the concept … Read More → "Synopsys Takes on RISC-V Configurability with ARC-V Processor IP Family"

Extremely Low Latency FPGAs and SmartNICs: How Achronix is Supercharging Networking Innovation

FPGAs take center stage in this week’s Fish Fry podcast! But not just any field programmable gate arrays – I’m talking about the Speedster7t FPGAs! My guests Scott Schweitzer and Ron Renwick from Achronix and I chat about why Achronix’s FPGAs are particularly well suited for networking and SmartNIC tasks, the advantages of Achronix’s accelerated network infrastructure code and the details of their new FPGA-Powered … Read More → "Extremely Low Latency FPGAs and SmartNICs: How Achronix is Supercharging Networking Innovation"

9.6Gbps HBM3 Memory Controller IP Boosts SoC AI Performance

It’s not often you get to say things like “exponential increase in insatiable demand,” so I’m going to make the most of it by taking a deep breath, pausing for effect, and waiting for the audience’s antici…

…pation to mount. As I’ve mentioned in previous columns (although possibly using different words), we are currently seeing an … Read More → "9.6Gbps HBM3 Memory Controller IP Boosts SoC AI Performance"

December 8, 2023
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December 6, 2023
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December 4, 2023
December 1, 2023
November 30, 2023

featured chalk talk

Challenges of Multi-Connectivity Asset Tracking
Multi-connectivity asset tracking is a critical element of our modern supply chain. In this episode of Chalk Talk, Colin Ramrattan and Manuel Cantone from STMicroelectronics and Amelia Dalton discuss the common needs required for asset tracking today, why low power processing is vital for these kind of applications, and how STMicroelectronics ASTRA platform can help you get started on your next asset tracking design.
Feb 20, 2023

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

Posted on Dec 8 at 7:42am by Karl Stevens
He should be careful at his age taking such long leaps to false conclusions. More than one of the current compilers use an abstract syntax tree and Roslyn/C# also provides an API. Evaluation of expressions is done using a stack. Now that he is gone with his proprietary analysis ...
Posted on Dec 7 at 10:35am by SmithChart
The power density here is truly awe inspiring. Getting watts of power out of something that small almost defies logic. No heat sinking even. Wow!
Posted on Dec 6 at 8:39pm by Steven Leibson
Great, theboom. Let me know when you've built one and offer it for sale. We'll be sure to cover it here in EEJournal.
Posted on Dec 6 at 6:35pm by theboom
Amazing! However, we are dreaming of a galvanically isolated, variable voltage, 5A converter, with similar footprint.
Posted on Dec 6 at 10:58am by Karl Stevens
aw Shucks!
Posted on Dec 6 at 8:52am by Steven Leibson
"However, there was Forth." That's a conversation ender, Karl. I don't discuss microprocessors or languages as religion.
Posted on Dec 6 at 7:18am by Karl Stevens
I fail to see the justification of primary other than that they can hide the validity of the studies. No, there are no "benchmark" applications.
Posted on Dec 6 at 7:12am by Karl Stevens
And every compiler utilizes a stack and not just for calls. For sure those were failures. However there was FORTH. And now there is C#(Roslyn) API and FPGAs come loaded with embedded true dual port memory blocks...that very few designers know how to use. And we both remember ...
Posted on Dec 6 at 2:55am by Shani
May I know what driving boards are used for Azumo 3.4” 64 Color Display? Can I have a schematic diagram of the driving board?
Posted on Dec 5 at 5:33am by Steven Leibson
No Karl, these studies are not published and are considered proprietary. It's called "do your own research." As for stack-based computers, HP during its many love affairs with strange processor architectures briefly fell in love with stack-based machines and implemented the original "classic" HP 3000 minicomputer as a stack machine. As ...
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featured blogs
Dec 8, 2023
Read the technical brief to learn about Mixed-Order Mesh Curving using Cadence Fidelity Pointwise. When performing numerical simulations on complex systems, discretization schemes are necessary for the governing equations and geometry. In computational fluid dynamics (CFD) si...
Dec 7, 2023
Explore the different memory technologies at the heart of AI SoC memory architecture and learn about the advantages of SRAM, ReRAM, MRAM, and beyond.The post The Importance of Memory Architecture for AI SoCs appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....
Dependable Power Distribution: Supporting Fail Operational and Highly Available Systems
Sponsored by Infineon
Megatrends in automotive designs have heavily influenced the requirements needed for vehicle architectures and power distribution systems. In this episode of Chalk Talk, Amelia Dalton and Robert Pizuti from Infineon investigate the trends and new use cases required for dependable power systems and how Infineon is advancing innovation in automotive designs with their EiceDRIVER and PROFET devices.
Dec 7, 2023
SLM Silicon.da Introduction
Sponsored by Synopsys
In this episode of Chalk Talk, Amelia Dalton and Guy Cortez from Synopsys investigate how Synopsys’ Silicon.da platform can increase engineering productivity and silicon efficiency while providing the tool scalability needed for today’s semiconductor designs. They also walk through the steps involved in a SLM workflow and examine how this open and extensible platform can help you avoid pitfalls in each step of your next IC design.
Dec 6, 2023
Reliable Connections for Rugged Handling
Materials handling is a growing market for electronic designs. In this episode of Chalk Talk, Amelia Dalton and Jordan Grupe from Amphenol Industrial explore the variety of connectivity solutions that Amphenol Industrial offers for materials handling designs. They also examine the DIN charging solutions that Amphenol Industrial offers and the specific applications where these connectors can be a great fit.
Dec 5, 2023
Must be Thin to Fit: µModule Regulators
In this episode of Chalk Talk, Amelia Dalton and Younes Salami from Analog Devices explore the benefits and restrictions of Analog Devices µModule regulators. They examine how these µModule regulators can declutter PCB area and increase the system performance of your next design, and the variety of options that Analog Devices offers within their Ultrathin µModule® regulator product portfolio.
Dec 5, 2023
Using the Vishay IHLE® to Mitigate Radiated EMI
Sponsored by Mouser Electronics and Vishay
EMI mitigation is an important design concern for a lot of different electronic systems designs. In this episode of Chalk Talk, Amelia Dalton and Tim Shafer from Vishay explore how Vishay’s IHLE power inductors can reduce radiated EMI. They also examine how the composition of these inductors can support the mitigation of EMI and how you can get started using Vishay’s IHLE® High Current Inductors in your next design.
Dec 4, 2023
Power Gridlock
The power grid is struggling to meet the growing demands of our electrifying world. In this episode of Chalk Talk, Amelia Dalton and Jake Michels from YAGEO Group discuss the challenges affecting our power grids today, the solutions to help solve these issues and why passive components will be the heroes of grid modernization.
Nov 28, 2023